To provide relatively high sampling rate analog to digital conversion, composite ADCs are typically used. A composite ADC contains a number of time interleaved sub-ADCs having a common input for receiving at the respective sub-ADCs, an applied to-be-converted analog signal. Same sampling rate sequential sampling timing signals are used to sample the analog signals applied to the inputs of the respective sub-ADCs. If the number of sub-ADCs equals M, then the resulting conversion rate is M times larger than the sampling rates of the individual sub-ADCs.
Each sub-ADC incorporated in a composite ADC, has its own distinct amplitude frequency response and phase frequency response, so that the amplitude frequency responses and phase frequency responses of the respective sub-ADCs are mutually misaligned. The misalignment of the frequency responses of the different sub-ADCs causes specific signal distortions at the digital signal output of the composite ADC, with the appearance of spurious frequency components being of prime importance. In order to reduce, or preferably, eliminate, the appearance of such spurious frequency components, outputs of the individual sub-ADCs are generally “equalized” and then combined, to provide an output for the ADC.
There are a number of ways in the prior art to prevent the appearance of distortions in a composite ADC, utilizing such equalization of the output digital signals of the sub-ADCs, as disclosed in several patents. For example, U.S. Pat. Nos. 7,079,992, 7,408,495 and 7,978,104, each propose an equalizer which is built as a time varying finite impulse response (FIR) filter. U.S. Pat. Nos. 5,239,299, 7,049,992, 7,541,958, 8,698,659 and others, describe an equalizer which is built as a set of switched FIR filters with constant coefficients. Both approaches (equalizers built as FIR filters with time varying coefficients, and equalizers built as a set of switched FIR filters with constant coefficients) are widely used in practice for equalization/correction of frequency responses of prior art composite ADCs.
FIG. 1 shows, in block diagram form, an example of a prior art ADC with equalization. The illustrated block diagram comprises a composite ADC 4, including a set of sub-ADCs, and a digital equalizer 5, which is built as a set of switched FIR filters with constant coefficients.
As shown, the Prior Art composite ADC 4 comprises M sub-ADCs, having a common input for receiving an analog signal-to-be-processed. The composite ADC 4 is characterized by a system clock signal at an overall sampling frequency Fs. Only three of the M sub-ADCs (denoted by reference designations sub-ADC #1, . . . , sub-ADC # m, . . . sub-ADC # M) are shown in FIG. 1, with the remaining sub-ADCs denoted by ellipses.
At each of the M sub-ADCs, the analog signal-to-be-processed is sampled at a sub-ADC sampling frequency Fs/M by an associated one of M mutually time-offset forms of the system clock signal. Each of the M sub-ADCs is characterized by an associated, but distinct, complex frequency response Gm(f), with m being the number of the sub-ADC, leading to the above-described misalignment-caused signal distortions at the output of the equalized Prior Art ADC.
The digital equalizer 5 of the Prior Art ADC attempts to effect equalization in order to offset the frequency response misalignment-caused distortions. As shown in FIG. 1, digital equalizer 5 consists of M sections, where each section includes M FIR filters. For example, section #1 comprises M FIR filters with reference designations FIR11, . . . , FIR1M. Outputs of those FIR filters are combined by an associated Adder, denoted Adder #1. The output of Adder #1 is connected to the output of the equalized ADC through a multiplexer switch MX1, which operates synchronously with sub-ADC #1. In the same manner, M-1 sections similar to section #1, are coupled between the other M-1 sub-ADCs and an associated one of the M-1 Adders, all of whose outputs are connected to the output of the equalized ADC.
By way of further clarification, the section with reference designation m also comprises M FIR filters, with reference numbers FIRm1, . . . , FIRmM. The outputs of those FIR filters are combined by Adder # m and the output of that adder is connected to the output of the equalized ADC through an associated multiplexer switch MXm. In general, the outputs of the composite ADC 4 are connected to the inputs of corresponding ones of the FIR filters of each section. The output of sub-ADC #1 is connected to the inputs of the FIR11, FIR21, . . . , FIRM1. The output of any sub-ADC # m (1≤m≤M) is connected to the inputs of the FIR1m, FIR2m, . . . , FIRMm.
The design of a prior art equalizer of a type such as that shown in FIG. 1, generally begins by a measurement of the frequency responses Gm(f) of the sub-ADCs for 1≤m≤M. The measured frequency responses Gm(f) then are used as initial data for calculation of the required frequency responses Hp,q(f) of the FIRp,q (1≤p≤M, 1≤q≤M). After that, the sets of coefficients of the different FIRs are calculated from the previously determined frequency responses Hp,q(f) by one of known methods (for example, known as the “windows” method, the “frequency-sampling” method, the “optimum equi-ripple” method and the “method based on least-squares” approach). The purpose of the design in the prior art, is to compensate the deviations of frequency responses Gm(f) from a chosen target frequency response. As a result, the misalignment between sub-ADCs frequency responses is eliminated or at least reduced, and the spurious frequency components are suppressed.
The principal components of FIR filters are multipliers. These multipliers have to operate with a frequency equal to the sampling rate Fs of the ADC, which at present time achieves tens of giga-samples per second (GS/s). At the same time, contemporary FPGAs, at best, operate at the frequencies in the range 200-250 MHz. As a result, each multiplication in an FIR filter in high-speed ADCs, requires tens or hundreds multipliers, connected in parallel. The required number of multipliers becomes the main reason, which makes it necessary to use in the design of equalizers, more FPGAs or FPGAs of larger size, and often makes it impossible to develop equalizers which can operate in the real time mode.
There is known in the art, a set of effective algorithms adapted for “fast filtering,” The application of such algorithms to an FIR filter allows a reduction in the number of multipliers in the FIR filter. These fast filtering algorithms (referred to hereinbelow as “Fast Filtering Algorithms”) originated in the basic work of S. Winograd “Arithmetic Complexity of Computations” (CBMS_NSF Regional Conf. Series in Applied Mathematics, SIAM Pub. 33, 1980) and have been developed farther in the articles of Z. Mou and P. Duhamel “Short-length FIR filters and Their Use in Fast Non-recursive Filtering” (IEEE Trans. on Signal Processing, vol. 19, No. 6, 1991), M. Vetterli “Running FIR and IIR Filtering Using Multirate Filter Banks” (IEEE Trans. Acoust., Speech, Signal Processing, vol. 36, No. 5, 1988) and others. According to the Fast Filtering Algorithms, any FIR filter with a length of L taps, may be replaced by an electrically equivalent compound unit, for example, of the type shown in FIG. 2, which is characterized by parameters K, K1 and K2.
An exemplary Fast Filtering Unit (“FFU”), shown in FIG. 2, includes a Pre-FIR transformer, a set of K sub-FIR filters FIR1, FIR2, . . . FIRK, and a Post-FIR Transformer. In particular, in the block diagram of FIG. 2, an input digital signal with a sampling rate Fs is initially processed in a Pre-FIR transformer. The Pre-FIR transformer produces K output signals, where each output signal has a reduced sampling rate Fs/K1. The outputs of the Pre-FIR transformer are connected to respective inputs of K sub-FIR filters FIR1, FIR2, . . . FIRK, where each FIR filter has a length L/K2 taps. The outputs of the respective K sub-FIR filters are connected to respective inputs of a Post-FIR transformer. The Post-FIR transformer processes its set of K input signals and forms an output signal of the Fast Filtering Unit. In general, an FIR filter with a length of L taps, performs L multiplications with the frequency Fs each. The K sub-FIR filters, FIR1, FIR2, . . . FIRK, in FIG. 2 perform K·L/K2 multiplications, each with frequency Fs/K1. With this structure and format, the equivalent compound unit of FIG. 2 which implements a Fast Filtering Algorithm, requires a number of multipliers, which is K1·K2/K times fewer than the number of multipliers required in a conventional FIR filter.
The parameters K, K1 and K2 depend on a specific Fast Filtering Algorithm, while the complex frequency response of the equivalent compound unit which replaces the inefficient original FIR filter, is determined by the coefficients of the sub-FIRs FIR1, FIR2, . . . FIRK of FIG. 2 that are used.
A digital equalizer for a composite ADC, built with the use of such a Fast Filtering Algorithm, was disclosed in U.S. Pat. No. 8,542,142 (the “'142 patent”) of the same inventors as in the subject invention. The equalized ADC of the '142 patent permits a reduction in the required number of multipliers in the equalizer compared to ADCs of the then-prior art. However, the equalizer disclosed in the '142 patent is constructed in the form of a filter with time varying coefficients. For that reason, it is necessary to use parallel processing of an input signal, splitting the input signal into leading N-groups and lagging N-groups, and adding to the design a repositioning unit and double buffer FIR filters with a consequent complication of the device.
The purpose of the present disclosure is to disclose a digital equalizer for a composite ADC which is obtained by applying a Fast Filtering Algorithm to an initial equalizer built as a set of switched FIR filters with constant coefficients. Such an approach makes it possible to reduce the number of multipliers in the equalizer as compared to the number off multipliers required in ADCs of the prior art, including the ADCs of the '142 patent. In that way the greatest possible reduction of the required resources is achieved.